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esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 1/34 flash 2.5v only 4 mbit serial flash memory with dual output ? features y single supply voltage 2.3~3.3v y standard, dual spi y speed - read max frequency: 33mhz - fast read max frequency: 50mhz; 86mhz; 100mhz - fast read dual max frequency: 50mhz / 86mhz/ 100mhz (100mhz / 172mhz/ 200mhz equivalent dual spi) y low power consumption - active current: 25 ma - standby current: 5 a - deep power down current: 3 a y reliability - 100,000 typical program/erase cycles - 20 years data retention y program - byte programming time: 7 s (typical) - page programming time: 1.5 ms (typical) y erase - chip erase time 3 sec (typical) - block erase time 0.75 sec (typical) - sector erase time 150 ms (typical) y page programming - 256 byte per programmable page y spi serial interface - spi compatible: mode 0 and mode 3 y end of program or erase detection y write protect ( wp ) y hold pin ( hold ) y all pb-free products are rohs-compliant ? ordering information product id speed package comments f25s04pa ?50pg 50mhz 8-lead soic 150 mil pb-free f25s04pa ?86pg 86mhz 8-lead soic 150 mil pb-free f25s04pa ?100pg 100mhz 8-lead soic 150 mil pb-free f25s04pa ?50pag 50mhz 8-lead soic 200 mil pb-free f25s04pa ?86pag 86mhz 8-lead soic 200 mil pb-free f25s04pa ?100pag 100mhz 8-lead soic 200 mil pb-free f25s04pa ?50dg 50mhz 8-pin pdip 300 mil pb-free f25s04pa ?86dg 86mhz 8-pin pdip 300 mil pb-free f25s04pa ?100dg 100mhz 8-pin pdip 300 mil pb-free f25s04pa ?50hg 50mhz 8-contact wson 6x5 mm pb-free f25s04pa ?86hg 86mhz 8-contact wson 6x5 mm pb-free f25s04pa ?100hg 100mhz 8-contact wson 6x5 mm pb-free
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 2/34 1 8 2 7 3 6 4 5 vdd hold sck si ce so wp vss ? general description the f25s04pa is a 4megabit, 2.5v only cmos serial flash memory device. the device supports the standard serial peripheral interface (spi), and a dual spi. esmt?s memory devices reliably store memory data even after 100,000 programming and erase cycles. the memory array can be organized into 2,048 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the page program instruction. the device features sector erase architecture. the memory array is divided into 128 uniform sectors with 4k byte each; 8 uniform blocks with 64k byte each. sect ors can be erased individually without affecting the data in ot her sectors. blocks can be erased individually without affecting the data in other blocks. whole chip erase capabilities provide the flexibility to revise the data in the device. the device has sector, block or chip erase but no page erase. the sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory. ? pin configurations 8- lead soic
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 3/34 1 8 2 7 3 6 4 5 vdd hold sck si ce so wp vss 8- pin pdip 8- contact wson 1 2 3 4 8 7 6 5 ce so wp vss vdd ho ld sck si
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 4/34 ? pin description symbol pin name functions sck serial clock to provide the timing for serial input and output operations si serial data input to transfer commands, addresses or data serially into the device. data is latched on the rising edge of sck. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of sck. ce chip enable to activate the device when ce is low. wp write protect the write protect ( wp ) pin is used to enable/disable bpl bit in the status register. hold hold to temporality stop serial communication with spi flash memory without resetting the device. vdd power supply to provide power. vss ground ? functional block diagram address buffers and latches x-decoder flash y-decoder i/o butters and data latches serial interface control logic ce sck si wp so hold
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 5/34 ? sector structure table 1: f25s04pa sector address table block address block sector sector size (kbytes) address range a18 a17 a16 127 4kb 07f000h ? 07ffffh : : : 7 112 4kb 070000h ? 070fffh 1 1 1 111 4kb 06f000h ? 06ffffh : : : 6 96 4kb 060000h ? 060fffh 1 1 0 95 4kb 05f000h ? 05ffffh : : : 5 80 4kb 050000h ? 050fffh 1 0 1 79 4kb 04f000h ? 04ffffh : : : 4 64 4kb 040000h ? 040fffh 1 0 0 63 4kb 03f000h ? 03ffffh : : : 3 48 4kb 030000h ? 030fffh 0 1 1 47 4kb 02f000h ? 02ffffh : : : 2 32 4kb 020000h ? 020fffh 0 1 0 31 4kb 01f000h ? 01ffffh : : : 1 16 4kb 010000h ? 010fffh 0 0 1 15 4kb 00f000h ? 00ffffh : : : 0 0 4kb 000000h ? 000fffh 0 0 0
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 6/34 ? status register the software status register prov ides status on whether the flash memory array is available for any read or write operation, whether the device is write enabl ed, and the state of the memory write protection. during an inter nal erase or program operation, the status register may be read only to determine the completion of an operation in progress. tabl e 2 describes the function of each bit in the software status register. table 2: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0 r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0 r 2 bp0 indicate current level of block write protection (see table 3) 0 r/w 3 bp1 indicate current level of block write protection (see table 3) 0 r/w 4 bp2 indicate current level of block write protection (see table 3) 0 r/w 5 tb top / bottom write protect 0 r/w 6 reserved reserved for future use 0 n/a 7 bpl 1 = bp2,bp1,bp0 and tb are read-only bits 0 = bp2,bp1,bp0 and tb are read/writable 0 r/w note: 1. only bp0, bp1, bp2, tb and bpl are writable. 2. bp0, bp1, bp2, tb and bpl are non-volatile. 3. all area are unprotected at power-on (bp2=bp1=bp0=0). write enable latch (wel) the write-enable-latch bit indicate s the status of the internal memory write enable latch. if this bi t is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/ erase) commands. th is bit is automatically reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? page program instruction completion ? sector erase instruction completion ? block erase instruction completion ? chip erase instruction completion ? write status register instructions busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for t he next valid operation. top/bottom block protect (tb) the top/bottom bit (tb) controls if the block-protection (bp2, bp1, bp0) bits protect from the top (tb=0) or the bottom (tb=1) of the array as show in table 3, the tb bit can be set with write status register (wrsr) instructi on. the tb bit can not be written to if the block- protection-look (bpl) bit is 1 or wp is low.
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 7/34 table 3: f25s04pa block protection table status register bit protected memory area protection level tb bp2 bp1 bp0 block range address range 0 x 0 0 0 none none upper 1/8 0 0 0 1 block 7 070000h ? 07ffffh upper 1/4 0 0 1 0 block 6~7 060000h ? 07ffffh upper 1/2 0 0 1 1 block 4~7 040000h ? 07ffffh lower 1/8 1 0 0 1 block 0 000000h ? 00ffffh lower 1/4 1 0 1 0 block 0~1 000000h ? 01ffffh lower 1/2 1 0 1 1 block 0~3 000000h ? 03ffffh all blocks x 1 x x block 0~7 000000h ? 07ffffh block protection (bp2, bp1, bp0) the block-protection (bp2, bp1, bp0) bits define the size of the memory area, as defined in tabl e 3, to be software protected against any memory write (progr am or erase) operations. the write status register (wrsr) in struction is used to program the bp2, bp1, bp0 bits as long as wp is high or the block- protection-look (bpl) bit is 0. chip erase can only be executed if block-protection bits are all 0. after power-up, bp2, bp1 and bp0 are set to 0. block protection lock-down (bpl) wp pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the tb, bpl, bp2, bp1, and bp0 bits. when the wp pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0.
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 8/34 ? hold operation hold pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold mode, ce must be in active low state. the hold mode begins when the sck active low state coincides with the falling edge of the hold signal. the hold mode ends when the hold signal?s rising edge coincides with the sck active low state. if the falling edge of the hold signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reac hes the active low state. see figure 1 for hold condition waveform. once the device enters hold mode, so will be in high impedance state while si and sck can be v il or v ih . if ce is driven active high during a hold condition, it resets the internal logic of the device. as long as hold signal is low, the memory remains in the hold condition. to resume communication with the device, hold must be driven active high, and ce must be driven active low. see figure 22 for hold timing. active hold active hold active hold sck figure 1: hold condition waveform ? write protection the device provides software write protection. the write-protect pin ( wp ) enables or disables the lock-down function of the status register. the block-protection bits (bp2, bp1, bp0, tb and bpl) in the stat us register provide write protection to the memory array and the status register. see table 3 for block-protection description. write protect pin ( wp ) the write-protect ( wp ) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp is driven low, the execution of the wr ite status register (w rsr) instruction is determined by the value of the bpl bit (see table 4). when wp is high, the lock-down function of the bpl bit is disabled. table 4: conditions to execute write-status-register (wrsr) instruction wp bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 9/34 ? instructions instructions are used to read, write (erase and program), and configure the f25s04pa. the inst ruction bus cycles are 8 bits each for commands (op code), dat a, and addresses. prior to executing any page program, wr ite status register, sector erase, block erase, or chip er ase instructions, the write enable (wren) instruction must be executed first. the complete list of the instructions is provided in table 5. all instructions are synchronized off a high to low transition of ce . inputs will be accepted on the rising edge of sck starting with the most significant bit. ce must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read id, read status register, read electronic signature instructions). any low to high transition on ce , before receiving the la st bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. instruction commands (op code), addresses, and data are all input from the most signi ficant bit (msb) first. table 5: device operation instructions bus cycle 1~3 1 2 3 4 5 6 n operation max. freq s in s out s in s out s in s out s in s out s in s out s in s out s in s out read 33 mhz 03h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x d out0 x d out1 x cont. fast read 0bh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x x x d out0 x cont. fast read dual output 11,12 3bh a 23 -a 16 a 15 -a 8 a 7 -a 0 x d out0~1 cont. sector erase 4 (4k byte) 20h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - - - block erase 4, (64k byte) d8h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - - - chip erase 60h / c7h hi-z - - - - - - - - - - - - page program ( pp ) 02h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in0 hi-z d in1 hi-z up to 256 bytes hi-z read status register ( rdsr ) 6 05h hi-z x d out - - - - - - - - - - write status register ( wrsr ) 01h hi-z d in hi-z - - -. - - - - - - - write enable ( wren ) 9 06h hi-z - - - - - - - - - - - - write disable ( wrdi ) 04h hi-z - - - - - - - - - - - - deep power down ( dp ) b9h hi-z - - - - - - - - - - - - release from deep power down ( rdp ) abh hi-z - - - - - - - - - - - - read electronic signature ( res ) 7 abh hi-z x x x x x x x 12h - - - - jedec read id ( jedec-id ) 8 9fh hi-z x 8ch x 30h x 13h - - - - - - 00h hi-z x 8ch x 12h - - read id ( rdid ) 10 50 mhz ~ 100 mh z 90h hi-z 00h hi-z 00h hi-z 01h hi-z x 12h x 8ch - - note: 1. operation: s in = serial in, s out = serial out, bus cycle 1 = op code 2. x = dummy input cycles (v il or v ih ); - = non-applicable cycles (cycles are not necessary); cont. = continuous 3. one bus cycle is eight clock periods. 4. sector earse addresses: use a ms -a 12 , remaining addresses can be v il or v ih block earse addresses: use a ms -a 16 , remaining addresses can be v il or v ih 5. to continue programming to the next sequential address location, enter the 8-bi t command, followed by the data to be programmed. 6. the read-status-register is continuo us with ongoing clock cycles until terminated by a low to high transition on ce . 7. the read-electronic-signature is contin uous with on going clock cycles until terminated by a low to high transition on ce . 8. the jedec-read-id is output first byte 8ch as manufacture id; second byte 30h as memory type; third byte 13h as memory capacity. 9. the write-enable (wren) instruction a nd the write-status-register (wrsr) instru ction must work in conjunction of each other. the wrsr instruction must be execut ed immediately (very next bus cycle) afte r the wren instruction to make both
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 10/34 instructions effective. wren can enable wrsr, user just need to execute it. a successful wrsr can reset wren. 10. the manufacture id and device id output will repeat continuously until ce terminates the instruction. 11. dual commands use bidirectional io pins. d out and cont. are serial data out; others are serial data in. 12. dual output data: io 0 =(d 6 ,d 4 ,d 2 ,d 0 ), (d 6 ,d 4 ,d 2 ,d 0 ) io 1 =(d 7 ,d 5 ,d 3 ,d 1 ), (d 7 ,d 5 ,d 3 ,d 1 ) d out0 d out1
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 11/34 ce sck si 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 40 4748 55 56 6 3 64 80 n+ 4 d ou t n+ 3 d ou t n+2 d out n+1 d out n d ou t msb msb msb high impenance so 0b add. add. a dd . mod e3 mode0 71 72 x no te : x = dummy byte : 8 clocks input dummy (v il or v ih ) read (33mhz) the read instruction supports up to 33 mhz, it outputs the data starting from the specified a ddress location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address spac e, i.e. for 4mbit density, once the data from address location 7ffffh had been read, the next output will be from address location 000000h. the read instruction is initiat ed by executing an 8-bit command, 03h, followed by address bits [a 23 -a 0 ]. ce must remain active low for the duration of the read cycle. see figure 2 for the read sequence. figure 2: read sequence fast read (50 mhz ~ 100 mhz) the fast read instruction suppor ting up to 100 mhz is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the fast read cycle. see figure 3 for the fast read sequence. following a dummy byte (8 clo cks input dummy cycle), the fast read instruction outputs the dat a starting from the specified address location. the data output st ream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4mbit density, once t he data from address location 7ffffh has been read, the next output will be from address location 000000h. figure 3: fast read sequence
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 12/34 fast read dual output (50 mhz ~ 100 mhz) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruct ion except the data is output on si and so pins. this allows data to be transferred from the device at twice the rate of sta ndard spi devices. this instruction is for quickly downloading code from flash to ram upon power-up or for applications that cache code- segments to ram for execution. the fast read dual output instru ction is initiated by executing an 8-bit command, 3bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the fast read dual output cycle. see figure 4 for the fast read dual output sequence. figure 4: fast read dual output sequence
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 13/34 page program (pp) the page program instruction allows many bytes to be programmed in the memory. the bytes must be in the erased state (ffh) when initiating a program operation. a page program instruction applied to a protected memory area will be ignored. prior to any write operation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the page program instruction. the page program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 -a 0 ]. following the address, at least one byte data is input (the maximum of input data can be up to 256 bytes). if the 8 least significant address bits [a 7 -a 0 ] are not all zero, all transmitted data that goes beyo nd the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [a 7 -a 0 ] are all zero). if more than 256 bytes data are s ent to the device, previously latched data are discarded and the last 256 bytes data are guaranteed to be programmed correctly within the same page. if less than 256 bytes data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. ce must be driven high before t he instruction is executed. the user may poll the busy bit in the so ftware status register or wait t pp for the completion of the internal self-timed page program operation. while the page program cy cle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. it is reco mmended to wait for a duration of t bp before reading the status regi ster to check the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished, the write-enable-latch (wel) bit in t he status register is cleared to 0. see figure 7 for the page program sequence. figure 7: page program sequence
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 14/34 64k byte block erase the 64k-byte block erase instruction clears all bits in the selected block to ffh. a block erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write enable (w ren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the block erase instruction is initiated by executing an 8-bit command, d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms = most significant address) are used to determine the block address (ba x ), remaining address bits can be v il or v ih . ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t be for the completion of the internal self-timed block erase cycle. see figure 8 for the block erase sequence. figure 8: 64k-byte block erase sequence 4k byte sector erase the sector erase instruction clears all bits in the selected sector to ffh. a sector erase instructi on applied to a protected memory area will be ignored. prior to an y write operation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the sector erase instruction is in itiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih . ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t se for the completion of the inte rnal self-timed sector erase cycle. see figure 9 for the sector erase sequence. ce sck si 012345678 15 16 23 24 31 msb msb high impenance so 20 add. add. add. mode3 mode0 figure 9: 4k-byte sector erase sequence
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 15/34 chip erase the chip erase instruction clears all bits in the device to ffh. a chip erase instruction will be ignored if any of the memory area is protected. prior to any write oper ation, the write enable (wren) instruction must be executed. ce must remain active low for the duration of the chip-erase instruction sequence. the chip erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip erase cycle. see figure 10 for the chip erase sequence. figure 10: chip erase sequence read status register (rdsr) the read status register (rdsr) instruction allows reading of the status register. t he status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce must be driven low before the rdsr instruction is entered and remain low until the status data is read. read status register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the ce . see figure 11 for the rdsr instruction sequence. figure 11: read status register (rdsr) sequence ce sck si 01234567 msb hi gh impenan ce so 60 or c7 mod e3 mode0
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 16/34 write enable (wren) the write enable (wren) instru ction sets the write-enable- latch bit in the software status register to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. ce must be driven high before the wren instruction is executed. figure 12: write enable (wren) sequence write disable (wrdi) the write disable (wrdi) instruct ion resets the write-enable- latch bit to 0 disabling any new write operations from occurring. ce must be driven high before the wrdi instruction is executed. figure 13: write disable (wrdi) sequence ce sck si 01234567 msb hi gh im penan ce so 06 mod e3 mode0 ce sck si 01234567 msb hi gh im penan ce so 04 mod e3 mode0
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 17/34 write-status-register (wrsr) the write status register instru ction writes new values to the bp2, bp1, bp0, tb and bpl bits of the status register. ce must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 14 for wren and wrsr instruction sequences. executing the write st atus register instruction will be ignored when wp is low and bpl bit is set to ?1?. when the wp is low, the bpl bit can only be set from ?0? to ?1? to lock down the status register, but cannot be reset from ?1? to ?0?. when wp is high, the lock-down function of the bpl bit is disabled and the bpl, tb, bp0, bp1,and bp2 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp pin is driven high (v ih ) prior to the low-to-high transition of the ce pin at the end of the wrsr inst ruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the tb, bp0; bp1 and bp2 bits at the same time. see table 4 for a summary description of wp and bpl functions. figure 14: write-enable (wren) and write-status-register (wrsr) ce sck si 01234567 msb msb high impenance so 06 mode3 mode0 76 5 4 32 1 0 01 0123456789 10 11 12 13 14 15 stauts register da ta in
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 18/34 deep power down (dp) the deep power down instruction is for minimizing power consumption (the standby current is reduced from i sb1 to i sb2 .). this instruction is initiated by executing an 8-bit command, b9h, and then ce must be driven high. after ce is driven high, the device will enter to deep power down within the duration of t dp . once the device is in deep power do wn status, all instructions will be ignored except the release from deep power down instruction (rdp) and read elec tronic signature instruction (res). the device always power-up in the normal operation with the standby current (i sb1 ). see figure 15 for the deep power down instruction. figure 15: deep power down instruction release from deep power down (rdp) and read-electronic-signature (res) the release form deep power down and read-electronic- signature instruction is a multi-purpose instruction. the instruction can be used to re lease the device from the deep power down status. this instruction is initiated by driving ce low and executing an 8-bit command, abh, and then drive ce high. see figure 16 for rdp inst ruction. release from the deep power down will take the duration of t res1 before the device will resume normal operation and other instructions are accepted. ce must remain high during t res1 . the instruction also can be used to read the 8-bit electronic- signature of the device on the so pi n. it is initiated by driving ce low and executing an 8-bit command, abh, followed by 3 dummy bytes. the electronic-signat ure byte is then output from the device. the electronic-signat ure can be read continuously until ce go high. see figure 17 for res sequence. after driving ce high, it must remain high during for the duration of t res2 , and then the device will resume normal operation and other instructions are accepted. the instruction is executed while an erase, program or wrsr cycle is in progress is ignored and has no effect on the cycle in progress. sck 01234567 mod e3 mode0 si ce standard current t dp msb b9 deep power down current (i sb 2 )
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 19/34 figure 16: release from deep power down (rdp) instruction figure 17: read electronic -signature (res) sequence table 6: electronic signature data command electronic signature data res 12h sck 01234567 mod e3 mode0 si ce standby current t res1 msb ab deep power down current ( i sb 2 ) so high impedance sck 0123456789 mod e3 mode0 si ce standby current t res2 msb ab deep power down current ( i sb2 ) so high impedance ss 30 31 32 3 3 34 35 36 37 38 ss electronic-signature data out ss msb 3dummybytes
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 20/34 jedec read-id the jedec read-id instructi on identifies the device as f25s04pa and the manufacturer as esmt. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, 8ch, is output from the device. after that, a 16-bit device id is shifted out on the so pin. byte1, 8ch, identifies the manufacturer as esmt. byte2, 30h, identifies the memory type as spi flash. byte3, 13h, identifies the device as f25s04pa. the instruction sequence is shown in figure 18. the jedec read id instruction is terminated by a low to high transition on ce at any time during data output. if no other command is issued after executing the jedec read-id instruction, issue a 00h (nop) command before going into standby mode ( ce =v ih ). figure 18: jedec read-id sequence table 7: jedec read-id data device id manufacturer?s id (byte 1) memory type (byte 2) memory capacity (byte 3) 8ch 30h 13h ce sck si msb high impenance so 9f mode3 mode0 01 23 45 67 89 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031 8c msb 30 13 msb msb
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 21/34 read-id (rdid) the read-id instruction (rdid) identifies the devices as f25 s04pa and manufacturer as esmt. this command is backward compatible to all esmt spi devices and should be used as default device identific ation when multiple versions of esmt spi devices are used in one design. the device information can be read from executing an 8-bit command, 90h, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 000000h and the device id is located in address 000001h. once the device is in read-id mode, the manufacturer?s and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on ce . figure 19: read-id sequence table 8: product id data address byte1 byte2 8ch 12h 000000h manufacturer?s id device id esmt f25s04pa 12h 8ch 000001h device id esmt f25s04pa manufacturer?s id ce sck si 012345678 15 16 23 24 31 32 39 40 47 4 8 55 56 63 msb msb high impenance so 90 0 0 00 add 1 mode3 mode0 note: the manufacture?s an d device id o utput stream i s continu ous until terminated by a low to high transition on ce. 1. 00h will output the manufacture?s id first a nd 01h will output device id first b efore toggling between the two. . high impena nce 8c 8c 12 12 msb
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 22/34 ? electrical specifications absolute maximum stress ratings (applied conditions are greater than those listed under ?a bsolute maximum stress ratings? may cause permanent damage to the dev ice. this is a stress rating only and functional operation of the device at these conditions or conditi ons greater than those define d in the operational sections of this datas heet is not implied. exposure to absolute maxi mum stress rating conditions may affect device reliability.) storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vdd+0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to vdd+2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma ( note 1: output shorted for no more than one se cond. no more than one output shorted at a time. ) ac conditions of test operating range parameter symbol value unit operating supply voltage v dd 2.3 ~ 3.3 v ambient operating temperature t a 0 ~ 70 table 9: dc operating characteristics limits symbol parameter min max unit test condition standard 3 i ddr1 read current @33 mhz dual 4 ma ce =0.1 v dd /0.9 v dd , so=open standard 6 i ddr2 read current @ 50mhz dual 8 ma ce =0.1 v dd /0.9 v dd , so=open standard 10 i ddr3 read current @ 86mhz dual 12 ma ce =0.1 v dd /0.9 v dd , so=open standard 20 i ddr4 read current @ 100mhz dual 25 ma ce =0.1 v dd /0.9 v dd , so=open i ddw program and erase current 15 ma ce =v dd i sb1 standby current 5 a ce =v dd , v in =v dd or v ss i sb2 deep power down current 5 a ce =v dd , v in =v dd or v ss i li input leakage current 2 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 2 a v out =gnd to v dd , v dd =v dd max v il input low voltage -0.5 0.3 x v dd v v dd =v dd min v ih input high voltage 0.7 x v dd v dd +0.4 v v dd =v dd max v ol output low voltage 0.4 v i ol = 1.6ma, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min input rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . . . . c l = 15 pf for R 75mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c l = 30 pf for Q 50mhz see figures 28 and 29
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 23/34 table 10: recommended system power-up timings symbol parameter minimum unit t pu-read 1 v dd min to read operation 10 s t pu-write 1 v dd min to write operation 10 s table 11: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 8 pf c in 1 input capacitance v in = 0v 6 pf note 1: this parameter is measured only for initial qualificati on and after a design or process change that could affect this p arameter. table 12: ac operating characteristics normal 33mhz fast 50 mhz fast 86 mhz fast 100 mhz symbol parameter min max min max min max min max unit f clk serial clock frequency 33 50 86 100 mhz t sckh 2 serial clock high time 13 9 5 4 ns t sckl 2 serial clock low time 13 9 5 4 ns t clch clock rise time (slew rate) 0.1 0.1 0.1 0.1 v/ns t chcl clock fall time (slew rate) 0.1 0.1 0.1 0.1 v/ns t ces 1 ce active setup time 5 5 5 5 ns t ceh 1 ce active hold time 5 5 5 5 ns t chs 1 ce not active setup time 5 5 5 5 ns t chh 1 ce not active hold time 5 5 5 5 ns t cph ce high time 100 100 100 100 ns t chz ce high to high-z output 6 6 6 6 ns t clz sck low to low-z output 0 0 0 0 ns t ds data in setup time 2 2 2 2 ns t dh data in hold time 5 5 5 5 ns t hls hold low setup time 5 5 5 5 ns t hhs hold high setup time 5 5 5 5 ns
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 24/34 table 12: ac operating characteristics - continued normal 33mhz fast 50 mhz fast 86 mhz fast 100 mhz symbol parameter min max min max min max min max unit t hlh hold low hold time 5 5 5 5 ns t hhh hold high hold time 5 5 5 5 ns t hz 3 hold low to high-z output 6 6 6 6 ns t lz 3 hold high to low-z output 6 6 6 6 ns t oh output hold from sck change 0 0 0 0 ns t v output valid from sck 12 8 8 8 ns t whsl 4 write protect setup time before ce low 20 20 20 20 ns t shwl 4 write protect hold time after ce high 100 100 100 100 ns t dp 3 ce high to deep power down mode 3 3 3 3 us t res1 3 ce high to standby mode ( for dp) 3 3 3 3 us t res2 3 ce high to standby mode (for res) 1.8 1.8 1.8 1.8 us note: 1. relative to sck. 2. t sckh + t sckl must be less than or equal to 1/ f clk . 3. value guaranteed by characteriza tion, not 100% tested in production. 4. only applicable as a constraint for a wr ite status register instruction when block- protection-look (bpl) bit is set at 1. erase and programming performance limit parameter symbol typ 2 max 3 unit sector erase time t se 150 300 ms block erase time t be 0.75 1.5 s chip erase time t ce 3.5 10 s write status register time t w 3 15 ms byte programming time t bp 7 30 us page programming time t pp 1.5 5 ms chip programming time 3 5 s erase/program cycles 1 100,000 - cycles data retention 20 - years notes: 1. not 100% tested, excludes external system level over head. 2. typical values measured at 25c, 2.5v. 3. maximum values measured at 85c, 2.3v.
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 25/34 figure 20: serial input timing diagram figure 21: serial output timing diagram
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 26/34 figure 22: hold timing diagram figure 23: write protect setup and hold timing during wrsr when bpl = 1 ce sck si high impenance so t whs l t shwl wp
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 27/34 time v cc v cc (max) v cc (min) v wi t puw t vsl reset state read command is allowed device is fully accessible program, erase and write command is ignored ce must track v cc figure 24: power-up timing diagram table 13: power-up timing and v wi threshold parameter symbol min. max. unit v cc (min) to ce low t vsl 10 us time delay before write instruction t puw 1 10 ms write inhibit threshold voltage v wi 1 2 v note: these parameters are characterized only.
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 28/34 figure 25: ac input/output reference waveforms figure 26: a teat load example input timing re f erence le v el output timing reference level 0.8vcc 0. 2vcc 0. 7v cc 0. 3vcc 0. 5v cc ac measurement level no te : i n p ut p ulse rise an d f all time are <5ns
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 29/34 packaging dimensions 8-lead soic ( 150 mil ) b e 0 l detail "x" a a1 seating plane d a2 l1 "x" c 1 4 e h 85 0.25 gauge plane dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a 1.35 1.60 1.75 0.053 0.063 0.069 d 4.80 4.90 5.00 0.189 0.193 0.197 a 1 0.10 0.15 0.25 0.004 0. 006 0.010 e 3.80 3.90 4.00 0.150 0.154 0.157 a 2 1.25 1.45 1.55 0.049 0. 057 0.061 l 0.40 0.66 0.86 0.016 0.026 0.034 b 0.33 0.406 0.51 0.013 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.203 0.25 0.0075 0.008 0.010 l 1 1.00 1.05 1.10 0.039 0.041 0.043 h 5.80 6.00 6.20 0.228 0.236 0.244 0 --- 8 0 --- 8 controlling dimension : millimenter
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 30/34 packing dimensions 8-lead soic 200 mil ( o fficial name ? 209 mil ) a1 a2 seating plane d b e e 1 4 8 5 detail "x" l1 l a e1 dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a --- --- 2.16 --- --- 0.085 e 7.70 7.90 8.10 0.303 0.311 0.319 a 1 0.05 0.15 0.25 0.002 0.006 0.010 e 1 5.18 5.28 5.38 0.204 0.208 0.212 a 2 1.70 1.80 1.91 0.067 0. 071 0.075 l 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0. 014 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.20 0.25 0.007 0.008 0.010 l 1 1.27 1.37 1.47 0.050 0.054 0.058 d 5.13 5.23 5.33 0.202 0.206 0.210 0 --- 8 0 --- 8 controlling dimension : millimenter
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 31/34 packing dimensions 8-pin p-dip ( 300 mil ) 14 85 d e 1 e e b a a 12 a seating plane e b b 1 l 0 dimension in mm dimension in inch symbol min norm max min norm max a 5.00 0.21 a 1 0.38 0.015 a 2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 bsc. 0.300 bsc. e 1 6.22 6.35 6.48 0.245 0.250 0.255 l 9.02 9.27 10.16 0.115 0.130 0.150 e 2.54 typ. 0.100 typ. e b 8.51 9.02 9.53 0.335 0.355 0.375 b 0.46 typ. 0.018 typ. b 1 1.52 typ. 0.060 typ. o 0 o 7 o 15 o 0 o 7 o 15 o controlling dimension : inch.
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 32/34 packing dimensions 8-contact wson ( 6x5 mm ) d2 e2 "a" d e "b" detail : "b" detail : "a" e a a1 b l pin# 1 pin# 1 symbol dimension in inch dimension in mm min norm max min norm max a 0.028 0.030 0.031 0.70 0.75 0.80 a1 0.000 0.001 0.002 0.00 0.02 0.05 b 0.014 0.016 0.018 0.35 0.40 0.45 d 0.232 0.236 0.240 5.90 6.00 6.10 d2 -- -- 0.161 -- -- 4.10 e 0.193 0.197 0.201 4.90 5.00 5.10 e2 -- -- 0.161 -- -- 4.10 e 0.050 bsc 1.27 bsc l 0.022 0.024 0.026 0.55 0.60 0.65 controlling dimension : millimeter
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 33/34 revision history revision date description 0.1 2009.02.20 original 0.2 2009.05.14 1. add dfn package 2. modify the test condition of v ol 0.3 2009.09.24 1. modify the specification of t se, t be , t ce, t bp, and t pp 2. rename dfn to wson 3. modify memory type code of jedec-id 4. correct the size of ?l? in the packaging dimensions of soic 150mil
esmt (preliminary) f25s04pa elite semiconductor memory technology inc. publication d ate : sep . 2009 revision : 0.3 34/34 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docum ent are believed to be accurate at the time of publication. esmt assu mes no responsibilit y for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of o ur products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. no license, either express, implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of esmt or others. any semiconductor devices may have i nherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

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